Receivers for wireless communications are being digitized in the sense that analog selectivity is being exchanged for digital processing and the ADC is gradually moving more towards the antenna. Wireless interconnectivity (for example, Bluetooth and IEEE 802.11x) and wireless cellular (for example GSM/EDGE, UMTS) seem prime candidates for adopting full-digital implementation of receiver baseband processing. Broadcast digital television (TV) is also a prime candidate. This is especially true for mobile digital TV standards such as DVB-H, ISDB-T, T-DMB, DVB-T, MediFLO.
The performance of multistandard receivers is directly influenced by the performance of the ADC. This leads to more and more demanding specifications for the required ADCs. Intensive on-going research on sigma-delta modulators or converters show the potential of sigma-delta converters as the most promising candidate for high-speed, high-resolution and low-power mixed-signal interfaces.
The sigma-delta converter architecture takes a fundamentally different approach than other ADC architectures. Sigma-delta converters generally consist of an integrator, a quantizer and a single-bit digital-to-analog converter (DAC). The DAC output is subtracted from the input signal and the resulting signal is integrated. The comparator converts the integrator output voltage to a single-bit digital output, e.g. “1” or “0”. The resulting bit becomes the DAC's input and the DAC's output is subtracted from the ADC's input signal. With such a sigma-delta architecture, the digital data from the ADC is a stream of ones and zeros, and the value of the signal is proportional to the density of digital “1”'s output by the quantizer. This bit stream data is then digitally filtered and decimated to result in a binary-format output. Thus, the sigma-delta converter circuit generates a 1-bit pulse density modulated (PDM) signal from an analog input signal. As an alternative, the sigma-delta converter circuit may as well generate a multi-bit output. This depends on the structure of the quantizer. If the quantizer is of a single-bit type, then the sigma-delta modulator generates a 1-bit output, but if the quantizer is of a multi-bit type, then the sigma-delta modulator generates a multi-bit stream. It creates fixed-width pulses in relation to the amplitude of the analog waveform. As the amplitude of the analog waveform rises, the first binary output value is produced. As it falls, the second binary output value is produced. If it remains neutral, alternating first and second binary output values are created.
The basic principle of sigma-delta converters involves trade-off between amplitude resolution and sampling rate. In contrast to other converter technologies such as Nyquist and Flash converters, sigma-delta converters sample signals much faster than the Nyquist sampling frequency (i.e. twice the bandwidth of the input signal). They offer high resolution achieved principally by their high-speed sampling combined with feedback, noise-shaping and digital filtering. Furthermore, sigma-delta converters offer the distinct advantage of lower power consumption. This is an important criterion especially with the proliferation of low-power mobile communication systems circuit, which means that the application areas for sigma-delta converters will grow.
FIG. 1 shows a schematic block diagram of a conventional highly analog receiver in which a radio frequency (RF) signal is received via an antenna and supplied via a low noise amplifier (LNA) 10 to a mixer circuit 20 where the received signal is converted to a low baseband frequency range. The baseband part of the receiver consists of an analog pre-filter section 30 which comprises a cascade of filter sections and programmable gain amplifiers (PGAs) required to limit the signal to a predefined level. The analog pre-filter section 30 is followed by a conventional sigma-delta ADC 40 which converts the analog input signal into a digital signal and supplies the digital signal to a digital filtering and scaling unit 50 from which it is supplied to a digital demodulation circuit 60.
However, the conventional architecture according to FIG. 1 leads to the disadvantage that the absence of preceding channel filtering implies that the input of the ADC 40 consists of both the wanted channel and a wide spectrum of possible interferer channels. As a consequence, both bandwidth and dynamic range of the ADC 40 must be extremely linear to prevent risk of intermodulation distortion by large interferers corrupting the reception of the wanted channel. As a result, energy consumption of the ADC 40 is high.
In view of the above disadvantage, Kathleen Philips et al., “A Continuous-Time ΣΔ ADC With Increased Immunity to Interferers”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, December 2004, presents a sigma-delta ADC with merged filtering and PGA. The described architecture describes a continuous-time sigma-delta ADC with a filtering signal transfer function (STF). This filtering STF makes the sigma-delta ADC immune to interferers even if they exceed the maximum allowable input level for the wanted channel.
FIG. 4 shows the STF of this conventional topology when designed for a GSM/EDGE application. It is flat within the conversion bandwidth, shows some overshoot for adjacent channels, and provides first-order filtering beyond the unity-gain frequency of the loop. The overshoot occurs due to the fast transition from nth-order to 1st-order behavior of the open loop gain and leads to the problem that adjacent channels are amplified towards the output. Considering that the allowable output modulation depth is fixed, this means that the stable input range for adjacent channels is smaller than that for the wanted channel.
FIG. 3 shows a schematic functional diagram of a switched capacitor (i.e. discrete time in contrast to continuous-time) delta-sigma ADC topology with reduced sensitivity to operation amplifier non-linearities, as described for example in J. Silva et al. “Wideband low-distortion delta-sigma ADC topology”, IEE Electronic letters, vol. 37, No. 12, 7th June 2001. Basically, the input X(z) is directly connected via a feedforward path 71 to an input of a quantizer or comparator 74 in order to create a flat STF without filtering capabilities. The digital output signal Y(z) is fed back via a DAC 76 and subtracted from the input signal X(z). An integration part with two transfer functions H1(z) and H2(z) and a coefficient of value “2” integrates the subtraction output and supplies the integrated signal to a summing point where it is summed with the input signal X(z). However, due to the dispensed filtering capabilities of the ADC of this solution, sufficient analog pre-filtering must be provided to prevent interferer from overloading the sigma-delta ADC.
However, analog components are critical in the sense that they introduced noise and distortion and thus degrade the signal-to-noise ratio and hence the receiver sensitivity. Moreover, their offset and gain or phase error accumulates and a lot of calibration and control loops are needed for correction. This increases design time, complexity and risks. Thus, it is desirable to digitize the received signal as early as possible.
In E. van der Zwan, “A 0.2 mW CMOS ΣΔ modulator for speech coding with 80 dB Dynamic Range”, IEEE. J. of Solid State Circuits; pp. 1873-1880 December 1996, a quantitative analysis of the anti-aliazing suppression of a continuous-time sigma-delta (ΣΔ) ADC is conducted. The described model captures feedforward and feedback sigma-delta topologies. It consists of a linear block comprising a loop filter transfer function G and two non-linear blocks: a 1-bit quantizer and a feedback DAC. An additional linearized model is described where the quantizer is replaced by a linearized gain c and an additive noise source Nq. a gain d, whereas the feedback DAC model is built with a linear gain d and a hold function.
Based on the linearized model, it is demonstrated that the alias component Zs at frequency Δf is attenuated by:
                                                  G            ⁡                          (                              mfs                -                                  Δ                  ⁢                                                                          ⁢                  f                                            )                                            G            ⁡                          (                              Δ                ⁢                                                                  ⁢                f                            )                                                                  (        1        )            where |G(f)| stands for the magnitude at frequency f of the loop filter transfer function G.
Additional wireless transmission systems, such as Bluetooth, may need to operate concurrently to other standards, because the wireless link between the radio terminal and other peripherals cannot be halted when voice or data communications are active, e.g., Bluetooth allows the use of wireless headphones during a cellular phone call. As a consequence, some traffic will co-exist in the ISM band (Industrial, Scientific, and Medical band) and in the cellular bands at the same time. This also applies to broadcast digital TV with the emergence of TV on Mobile. It is noted that in a multi-mode/multi-band receiver, the ISM, UHF, and cellular bands data will be received on a common multi-band antenna as illustrated in a receiver architecture of FIG. 10. It is noted that the L-band and S-band are also used for TV on Mobile applications.
FIG. 10 shows a multi-mode/multi-band receiver concept built on multi-band antenna 12 and ZIF (Zero Intermediate Frequency) receiver 22 for a 3G communication pipe. Signals received via the multi-band antenna 12 are supplied to a filter bank 16 comprising parallel filters for different receiving bands (Bands I to IV, GSM, UMTS, Bluetooth). Although not shown in FIG. 10, filters for other receiving bands such as UHF (Ultra High Frequency) or other broadcast bands may be provided as well or as an alternative. Bluetooth signals received within the Bluetooth reception band and are supplied to a Bluetooth receiver 18. Other signals received within a predetermined frequency band manually selected by the selection switch 14 are received through the respective filter of the filter bank 16. Then, the received and filtered signal is amplified by a respective one of a plurality of Low Noise Amplifiers (LNAs) 10 and supplied to the ZIF receiver 22 for digital band selection, which comprises in-phase (I) and quadrature-phase (Q) mixers 20 for generating I and Q components of the received signal by using reference signals from a tunable local oscillator. The I and Q components are processed in respective tunable filters, sigma-delta ADCs, and decimation filters.
The so-called 3G DigRF standard imposes some data-rate constraints for the data transfer between the radio frequency integrated circuit (RF-IC) and the baseband integrated circuit (BB-IC) for 3G (3rd generation) standard, e.g., Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), etc. As a result, 312 or 416 MHz sampling frequency (mfs) is required to clock the UMTS sigma-delta ADC. Consequently, some Bluetooth channels can alias in some cellular bands, i.e. can generate intermodulation frequencies within some cellular bands. For example, assuming that a Bluetooth channel is provided at 2404 MHz, a UMTS channel is provided at 1988 MHz (Band II) and the mfs is set at 416 MHz. The 2404 MHz Bluetooth channel is downconverted to 416 MHz (=2404 MHz-1988 MHz) by the UMTS ZIF (Zero Intermediate Frequency) receiver. During the A/D conversion process, the down-converted Bluetooth channel is sampled at mfs=416 MHz. By doing so, the frequency of the generated Bluetooth alias component is exactly on top of the frequency of the 3G wanted signal. Thus, without anti-aliazing (AA) filtering in front of the ADC, the SNR (signal-to-noise ratio) and BER (bit error rate) are seriously degraded.
FIG. 11 shows a table of cellular bands that can be potentially affected by SNR and BER limitations due to some ISM channel aliazing in the band of interest when the ADC is clocked at 312 MHz and 416 MHz. The following abbreviations are used in the table: EU=Europe, JP=Japan, APAC=Asia Pacific, AM=AMERICA. As indicated in the left two columns of the table, alias is generated in bands I and IV when the ADC is clocked at mfs=312 MHz and in band II when the ADC is clocked at mfs=416 MHz. It is worth noting that this issue concerns all locations in the world.
Generally speaking, co-existence of data traffic in cellular and ISM bands requires anti-aliazing means or provisions to be provided at the ADC.